![]() ![]() These processors are being used in desktop systems that have two, four, or eight processors on the same memory bus, and therefore incur all the shared memory problems of traditional large multiprocessor systems. Processors such as the Pentium Pro/II, Power PC 603 and 604, and the Digital Alphas are being built to include symmetric multiprocessor (SMP) support, especially in the form of cache coherence hardware in the cache. The first is the move towards supporting multiprocessor systems on-chip with current microprocessors. Two trends in computing are making cache coherency a more important issue in desktop computing. This implies that as the gap between main memory and multi-chip module latency increases this functionality can improve performance. We found that actual performance gain is heavily dependent upon actual system specifications, but there are definite indications of improvement, up to 66% on some benchmarks. ![]() Then, using our knowledge of current bus configurations, we will generate timing models to show the improvement in performance. We will test this by instrumenting multi-threaded code that might be run on these systems, and running it through a multiple cache simulator in order to obtain statistics on shared data references. Specifically, we believe that implementing cache-to-cache transfers on MESI coherence protocols will reduce miss latency, and multithreaded programs will benefit from this reduction because of the large amount of shared data between processors, in significantly improving performance. We feel there are cache optimizations that can be used to improve performance on these off-the-shelf SMP systems. These systems differ from larger vector processing machines in that they are still latency limited rather than bandwidth limited, especially when integrated onto a single multi-chip module. There has been an increasing trend towards small n-way SMP systems running multithreaded programs and operating systems. Optimizing the MESI Cache Coherence Protocol for Multithreaded Applications on Small Symmetric Multiprocessor SystemsÄepartment of Electrical and Computer Engineering Optimizing the MESI Cache Coherence Protocol for Multithreaded Applications on Small Symmetric Multiprocessor Systems 18-742 Class Project Information ![]()
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